In distributed processing systems, multiple processors communicate with each other and with memory devices to perform a shared computation. Because the types of computations involved are generally very complex or require a great deal of processing power, this type of communication must be very high speed. Therefore, it is generally accomplished using high-speed local data networks. In high-performance computing (“HPC”) systems, further speed increases are achieved using specialized hardware that is not generally available commercially off-the-shelf for use in, for example, desktop or server computers. This specialized hardware includes application-specific integrated circuits (“ASICs”) having a number of communications channels for communicating with each other, and with the processors, memory, and other specialized hardware unique to such tightly-coupled systems.
Communications protocols are defined to permit these various devices to communicate with one another. For instance, Intel Corporation of Santa Clara, Calif. has offered processors that communicate using the Intel® QuickPath Interconnect (“QPI”) protocol, and Advanced Micro Devices, Inc. of Sunnyvale, Calif. has offered processors that communicate using the HyperTransport protocol developed by the HyperTransport Consortium, also of Sunnyvale, Calif. HPC manufacturers may design ASICs to communicate using these protocols, or define high speed, low latency protocols for their ASICs to use with one another, or with other HPC hardware. The communications protocol between the ASIC and a processor or a memory may be modeled as a finite state machine.
HPC systems are generally custom-built and manufactured to provide the fastest hardware capabilities possible. Therefore, the ASICs of HPC systems known in the art execute protocol tables that are encoded directly into hardware. Hard-wired tables are advantageous for their high speed. However, if the tables are incorrectly designed or their hardware is incorrectly manufactured, they require new chips to be fabricated at considerable expense and delay in time-to-market. Moreover, some devices with which an ASIC may communicate may not conform to published protocol specifications, again due to poor design or manufacturing of these devices. In this situation, even if the ASIC was designed to perfectly implement the published protocol, and even if the ASIC was fabricated perfectly, it will still encounter protocol errors due to flaws in the device with which it is communicating.